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| 74F533 Octal Transparent Latch with 3-STATE Outputs April 1988 Revised August 1999 74F533 Octal Transparent Latch with 3-STATE Outputs General Description The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted. Features s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373 Ordering Code: Order Number 74F533SC 74F533SJ 74F533PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols IEEE/IEC Connection Diagram (c) 1999 Fairchild Semiconductor Corporation DS009548 www.fairchildsemi.com 74F533 Unit Loading/Fan Out U.L. Pin Names D0-D7 LE OE O0-O7 Description HIGH/LOW Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary 3-STATE Outputs 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -3 mA/24 mA (20 mA) Function Table Inputs LE H H L X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Functional Description Output D H L X X O L H O0 Z The 74F533 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. OE L L L H Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F533 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65C to +150C -55C to +125C -55C to +150C Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 41 -60 4.75 3.75 -0.6 50 -50 -150 500 61 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 0.5 50 V A A mA A V A mA A A mA A mA Min Max Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VIN = 5.5V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH Z 3 www.fairchildsemi.com 74F533 AC Electrical Characteristics TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 4.0 2.5 5.0 3.0 2.0 2.0 1.5 1.5 VCC = +5.0V CL = 50 pF Typ 6.7 4.4 7.1 4.7 5.9 5.6 3.4 2.7 Max 9.0 7.0 11.0 7.0 10.0 7.5 6.5 5.5 TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 4.0 2.5 5.0 3.0 2.0 2.0 1.5 1.5 Max 12.0 9.0 14.0 9.0 12.5 10.5 8.5 7.5 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 4.0 2.5 5.0 3.0 2.0 2.0 1.5 1.5 Max 10.0 8.0 13.0 8.0 11.0 8.5 7.0 6.5 ns Units ns ns ns AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH 2.0 2.0 3.0 3.0 6.0 Max TA = -55C to +125C VCC = +5.0V Min 2.0 2.0 3.0 3.0 6.0 Max TA = 0C to +70C VCC = +5.0V Min 2.0 2.0 3.0 3.0 6.0 Max ns ns ns Units www.fairchildsemi.com 4 74F533 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74F533 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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